1. Field of the Invention
This invention relates to a silicon carbide (SiC) semiconductor device, particularly to an insulation gate type field effect transistor such as a vertical power MOSFET for high power applications, and to a method of manufacturing the same.
2. Description of the Related Art
The applicant of the present invention proposes a planar type MOSFET capable of improving channel mobility to reduce an ON resistance in JP-A-10-308510 published on Nov. 17, 1998.
Referring to FIG. 12, the planar type MOSFET has an n.sup.+ type semiconductor substrate 1 made of SiC and having a main surface 1a at an upper side of the figure and a back surface 1b at a lower side of the figure. An n.sup.- type epitaxial layer (herebelow, referred to as an epi-layer) 2 made of SiC and having a dopant concentration smaller than that of the substrate 1 is disposed on the main surface 1a of the substrate 1.
Several p type base regions 3 are provided in specific surface portions of the n.sup.- type epi-layer 2 with a specific depth. The p type base regions 3 include boron (B) as a dopant with a dopant concentration of approximately 1.times.10.sup.17 cm.sup.-3 or more. Several n.sup.+ source regions 4 are formed in specific surface portions of the p type base regions 3 with a depth shallower than that of the p type base regions 3. An n.sup.- type SiC layer 5 extends in the surface portions of the p type base regions 3 to connect the n.sup.+ type source regions 4 and the n.sup.- type epi-layer 2. The n.sup.- type SiC layer 5 is epitaxially grown on the substrate 1 to have a 4H, 6H, 15R or 3C crystal structure. A channel is formed in then n.sup.- type SiC layer 5 when the device is operated. Herebelow, the n.sup.- type Sic layer 5 is referred to as a surface channel layer.
The surface channel layer 5 includes nitrogen (N) as a dopant with a dopant concentration in a range of, for example, 1.times.10.sup.15 cm.sup.-3 to 1.times.10.sup.17 cm.sup.-3, which is lower than those of the n.sup.- type epi-layer 2 and the p type base regions 3, thereby realizing a low ON resistance. A part of the n.sup.- type epi-layer 2 extending between the p type base regions 3 is a so-called J-FET portion 6.
A gate oxide film 7 is formed on the surface channel layer 5 and on the n.sup.+ type source regions 4 by thermal oxidation, and a gate electrode 8 is formed on the gate oxide film 7. The gate electrode 8 is covered with an insulation film 9 made of LTO (Low Temperature Oxide). A source electrode 10 is formed on the insulation film 9 in contact with the n.sup.+ type source regions 4 and the p type base regions 3. A drain electrode 11 is formed on the back surface 1b of the substrate 1.
This planar type MOSFET is operated in an accumulation mode at which a channel is induced without inverting the conductive type of the surface channel layer 5. In the accumulation mode, the surface (channel) mobility is less influenced by the electric field (gate) and surface effects (MOS interface) compared to the inversion mode due to a large depth of the channel (about 5-10 times). Therefore, channel mobility of the MOSFET is large, so that the ON resistance is reduced as compared to that of a MOSFET, which is operated in an inversion mode at which the conductive type of the surface channel layer is inverted. However, when B is used as a dopant for forming the p type base regions 3, B is diffused during heat treatment, such as during activation annealing as disclosed in U.S. Pat. No. 5,710,059. Diffused B can narrow the width of the J-FET portion, and undesirably invert the conductive type of the surface channel layer 5 contacting the p type base regions 3.